Sector-erase architecture
First generation devices like
EPROMs required bulk erasing; meaning you had to erase the entire memory array
before you could reprogram it with new data. Sector-erase architecture
eliminates that time-consuming task by subdividing the array into smaller
sections that can be independently erased. This allows for design flex-ibility,
and time reduction for code changes.
Some Flash devices are organized as
uniform sectors with each sector the exact same size. Changes you make are
effected in certain areas of the array. Although program changes are not made
often, you may want to change some parameters or some data. This prompted the
division of the memory section into smaller sections so that the system
designer has a variety of sector sizes avail-able— the so-called boot sectors.
Depending on the microprocessor being interfaced to the Flash device, you may
want those smaller boot sectors at the top or at the bottom of the address
range, hence top boot and bottom boot sector options. The sectors can be erased
individually or in groups without affecting the data in other sectors. When you
reprogram the memory, you don’t want to lose its data. Therefore, you first
read it out into RAM to temporarily hold the data, modify the array bytes in
the RAM, erase that sector or sectors in the Flash memory, and then reprogram
that sector or sectors using the modified data in the RAM.
Sector protection
Sector
protection, closely associated with sector erase, prevents inadvertent or
malicious writes into the array. The sector protect operation disables both
programming and erase operations in any combination of sectors of the Flash
memory array. This feature is enabled by using programming equipment, although
some devices allow this to be done in-system using a special algorithm and
high-voltage. Flash devices are usually shipped from the vendor’s factory with
all sectors unprotected. The current state of the protection circuitry can be
verified in the circuit by using the ‘Sector Protect Verify’ command available
on many flash memory devices. There is also a temporary sector unprotect
feature that allows the protect feature to be temporarily suspended to change
data in a pro-tected sector in-system. It is activated by setting the /RESET
pin to VID (11.5V to 12.5V). Once VID is re-moved, all previously protected sectors
will be protected again.
Simplifying programming
Cycling
endurance of a Flash device can be affected by improper program-ming or
erasing, even in systems that appear error free in development. An embedded or
automatic programming algorithm eliminates this issue and simplifies complex
programming procedures for Flash memories. Other advantages include reduced
system overhead and improved program/erase time. Embedded algorithms are
automatic, thus the system CPU is free to perform other functions during write
and erase operations. Moreover, these algorithms are designed such that
write/erase operations are performed in the most efficient way possible.
Erase suspend/resume
In
earlier devices, once the erase operation was initiated, it could not be
halted. Since an entire sector must be erased, erase time can be in the order
of seconds; hence, system designers had to wait until the erase operation was
completed before executing another operation. As the name implies, erase
suspend allows you to temporarily stop that opera-tion and go to read data from
or program data into other sectors that are not being erased. Erase suspend can
be kept on hold for microseconds or for days. It remembers its spot in the
algorithm and when deactivated via the erase resume command, it resumes the
erase operation from where it left off. You can erase suspend and resume
multiple times during an erase operation.
Erase suspend/resume
In
earlier devices, once the erase operation was initiated, it could not be
halted. Since an entire sector must be erased, erase time can be in the order
of seconds; hence, system designers had to wait until the erase operation was
completed before executing another operation. As the name implies, erase
suspend allows you to temporarily stop that opera-tion and go to read data from
or program data into other sectors that are not being erased. Erase suspend can
be kept on hold for microseconds or for days. It remembers its spot in the
algorithm and when deactivated via the erase resume command, it resumes the
erase operation from where it left off. You can erase suspend and resume
multiple times during an erase operation.
Single-supply operation
Single-supply operation is the
driving force that allows Flash to be used cost-effectively and in a simple way
in system designs. First genera-tion Flash devices required that the high voltage
needed for program and erase operations, usually 12V, be carefully waveshaped
and controlled in order to preserve device reliability. The high voltage, and
its waveshaping, is still required, but it is now generated internally through
a charge pump or high-voltage genera-tor in the Flash chip. Single-supply
devices perform read, erase, and programming functions using only a single Vcc
power supply (3V or 5V for current technology products). The command set used
to perform internal operations including erase and program was developed for
single-supply Flash at a time when there was a thorough understanding of
inadvertent write protection (IWP) issues. Thus, today’s single-supply Flash
provides a good degree of protection against inadvertent writes. This includes
the byte lock technique that protects every byte against inadvertent writes.
Every program or erase operation must first unlock the device to invoke the
operation. The key to ensured IWP is the sequence of specific address/data
writes to the device to control the internal control-ler to perform a program
or erase operation.
Device status indicators
With first generation Flash
devices, you could perform only one operation at a time: reading data, erasing
it, or programming it. If you wanted to read data from the device, you had to
determine when a previous erase or program operation was completed. The typical
procedure was to time the operation via your software and then verify
completion by testing the Flash device. Devices that include embed-ded or
automatic algorithms also incorporate status indication features to notify the
system designer when an operation is complete. There are several, including
ready/busy (RY// BY), Toggle Bit, and Data Bar Polling. The RY//BY open-drain
output pin is used to indicate to the host system that an internal programming
or erase operation is either in progress or has been completed. The RY//BY
output goes high when an erase operation is
suspended and returns to low when it is resumed. The Toggle Bit (DQ6)
indicates the status of the internal programming and erase algorithms. During a
programming or erase algorithm cycle, successive reads of data from the device
result in DQ6 toggling between one and zero. Once an internal programming or
erase operation is completed, DQ6 stops toggling and valid data is read on the
next read operations. Data Bar Polling (DQ7) also serves the same purpose. When
a byte/word programming operation is in progress, a device read produces the
comple-ment of the data last written to DQ7. When the programming operation is
completed, a device read produces the true data last written to DQ7. When chip
erase or sector erase is in progress, a read of the device pro-duces a logical
“0” at the DQ7 output. When chip erase or sector erase is completed, a read of
the device produces a logical “1” at the DQ7 output.
Simultaneous read/write
Simultaneous read/write allows
reading from a sector at the same time as a program or erase operation is
taking place in another sector. As stated earlier, traditional Flash only does
one operation at a time. It can either read, program, or erase. It can perform
one of three operations, but any two cannot be performed simulta-neously. In
some applications, this is not acceptable. In these cases, the system engineer
must have the capability of reading and program-ming at the same time. The
earlier approach to this issue was to use two memories. A cell phone is the
classic applica-tion for simultaneous read/write. To program a new number in
memory, the user presses a button on the handset to program and store that
number. However, the user does not want his or her phone to stop operating when
it is in the process of storing that new number. Therefore, up until recently,
a Flash device was used for the operating program and a second, smaller EEPROM
or other non-volatile device was used to hold the address book. One memory
could write while the other one read. Flash devices endowed with simultaneous
read/write can read data during program or erase operations. These devices
divide the chip into two banks of memory sectors. Each can perform operations
independent of the other, except that simultaneous program operations are not
permitted. By storing operating code in one bank and data in the other, there
is no need to interrupt program or erase opera-tions to read code.
Consequently, system engineers can omit other devices like EEPROMs and SRAMs,
thereby increasing system reliability and reducing total system cost.
Page and burst modes
Past generations of Flash devices
operated by reading a byte/word at a time, with each read operation requiring a
specified access time. Today’s high-performance micropro-cessors are designed
so that bursts of data can be accepted and handled appropriately. To match this
character-istic, some new Flash devices incor-porate a mechanism that allows
such a page of data, comprising a number of bytes or words, to be
simultaneously loaded into an output buffer from the Flash array. The data
stored in that buffer can be accessed/read quickly since it is not necessary to
fetch the data from the array again, eliminating the process where most of the
access time is consumed. Two types of memories that operate in this way are
page mode devices and burst mode devices. Both of these types have a long
initial access time (about 75ns), followed by faster access to other locations
within the page stored in the buffer (20ns to 25ns). The page mode device
allows asynchronous (no clock signal) random access to any byte/ word in the
current page, and a typical device has a page size of 16 bytes or eight words.
A burst mode device requires a synchronizing clock, and provides sequential
access to 32 words of data starting at a specified initial address. Hence,
average access time in both types of devices is very fast, making them suitable
for use in high-performance system designs; reading the first byte at 75ns and
the next 31 bytes at 20ns, average access time is about 20ns. Applications that
require the random access feature of page mode Flash include printers, and
network interface cards. Burst mode Flash, on the other hand, is ideally suited
for such applications as automotive, telecom, and internetworking. High-end
cell phone applications, in particular, are beginning to exploit the
performance dividends of burst mode Flash. Handset manufacturers are opting for
the higher performance burst mode provides compared to standard Flash. Three
control pins are added to burst mode Flash devices. They allow easy interfacing
to a wide range of microprocessors with minimal glue logic. These three pins
are Load Burst Address (LBA#), Burst Address Advance (BAA#), and Clock (CLK).
Common Flash Interface
The
Common Flash Interface (CFI) specification is aimed at storing a large amount of
data on the chip. You can think of CFI as a data book on a chip. It allows one
set of software drivers to identify and use a variety of different, current,
and future Flash devices. All identifying data for the device is directly
stored on the chip. CFI carries such data as memory size, timing data,
byte/word configu-ration, sector sizes, sector and block organizations,
features such as page or burst mode and simultaneous read/ write, and the basic
algorithm the device follows, among several other parameters. Before leading
Flash vendors adopted CFI, vital Flash data was stored in tables in system
soft-ware. When a new device was released, software generally had to be
modified to include a new table of data describing the new device. Hence, a
software designer who anticipated a future upgrade needed to incorporate
specific device informa-tion for any Flash component ex-pected to be designed
in during a system’s lifecycle. The intent of CFI is to eliminate the need to
modify software each time there is a change in Flash vendors or a new Flash
generation with new features is used. Regarded as a breakthrough in Flash
identification, CFI makes Flash de-vices interchangeable and encourages
adoption of new Flash technologies. Before leading Flash vendors adopted CFI,
vital Flash data was stored in tables in system software. When a new device was
released, software generally had to be modified to include a new table of data
describ-ing the new device. This table is resident in the software. Hence, a
software designer who anticipated a future upgrade needed to incorporate
specific device information for any Flash component expected to be designed in
during a system’s lifecycle. Flash devices have a unique set of capabilities,
which have made them the non-volatile memory of choice for a vast number of
designs in all major application segments. New features have been embodied into
the latest generations of devices to reduce system cost and complexity, and to
make them easier to use and better suited for today’s high-performance system
requirements.